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How to design 8 by 1 Multiplexer (Mux) ?

How to design 4 by 1 Multiplexer (Mux) ?

VERILOG HDL Codes

How to design 4 by 1 Multiplexer (Mux) ?

//Module :

module Four_To_One_Mux(
output out,
input i0,
input i1,
input i2,
input i3,
input s1,
input s0
);
wire s1n,s0n;
wire y0,y1,y2,y3;
not(s1n,s1);
not(s0n,s0);
and a0(y0,i0,s1n,s0n);
and a1(y1,i1,s1n,s0);
and a2(y2,i2,s1,s0n);
and a3(y3,i3,s1,s0);
or o1(out,y0,y1,y2,y3);
endmodule

 

//Test Module :

module Test_Four_To_One_Mux; 
reg I0,I1,I2,I3;
reg S1,S0;
wire OUTPUT;
Four_To_One_Mux mymux(OUTPUT,I0,I1,I2,I3,S1,S0);
initial
begin
I0=1;I1=0;I2=0;I3=1;
#1 $display (“I0=%b,I1=%b,I2=%b,I3=%b\n”,I0,I1,I2,I3);
S1=0;S0=0;
#1 $display (“S1=%b,S0=%b,OUTPUT=%b\n”,S1,S0,OUTPUT);
S1=0;S0=1;
#1 $display (“S1=%b,S0=%b,OUTPUT=%b\n”,S1,S0,OUTPUT);
S1=1;S0=0;
#1 $display (“S1=%b,S0=%b,OUTPUT=%b\n”,S1,S0,OUTPUT);
S1=1;S0=1;
#1 $display (“S1=%b,S0=%b,OUTPUT=%b\n”,S1,S0,OUTPUT);
end
endmodule

how-to-design-4-by-1-mux ?

2 Comments

  1. Ahmed Hannan says:

    Keep up the good work. Thumbs up!

  2. Codingknack says:

    Happy to help!

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