VERILOG HDL

Get started with Verilog HDL

What is Verilog ?

Verilog is a Hardware Description Language; a textual format for describing electronic circuits and systems. Applied to electronic design, Verilog is intended to be used for verification through simulation, for timing analysis, for test analysis (testability analysis and fault grading) and for logic synthesis.

The Verilog HDL is an IEEE standard – number 1364. The first version of the IEEE standard for Verilog was published in 1995. A revised version was published in 2001; this is the version used by most Verilog users. The IEEE Verilog standard document is known as the Language Reference Manual, or LRM. This is the complete authoritative definition of the Verilog HDL.

Level of Abstractions (Modeling Styles)

1:Gate Level Modeling

2:Data Flow Modeling

3:Behavioral Modeling

Gate Level Modeling :

  • In Gate level modeling circuits can be defined by using the logic gates.
  • It is pre-defined in Verilog library

Examples:

  1. and a1 (output, input);
  2. nand n1 (output, input);
  3. or 01 (output, input);
  4. not n2 (output, input);

Data Flow Modeling :

  • In Data float modeling circuits can be defined by using the equations.
  • The keyword used for it is assign.

Examples:

  1. assign  c = a+b; 
  2. assign  b = ~a; // not gate
  3. assign  c = a&b; // and gate
  4. assign  c = a>>1; // shift right c by 1

 

Behavioral Modeling :

Behavioral models in Verilog contain procedural statements, which control the simulation and manipulate variables of the data types. These all statements are contained within the procedures.

Examples:

module behave; 
reg [1:0]a,b; 

initial 
begin 
   a = b1; 
   b = b0; 
end 

always 
begin 
   #50 a = ~a; 
end 

always 
begin 
   #100 b = ~b; 
end 
End module